Electronic device

ABSTRACT

According to one embodiment, the interconnect layer includes a fourth conductive member and a fifth conductive member. The fourth conductive member is provided between the first region of the first chip and the third region of the second chip. The fourth conductive member connects the first conductive member of the first chip and the second conductive member of the second chip. The fifth conductive member is provided between the second region of the first chip and the fifth region of the third chip. The fifth conductive member connects the first conductive member of the first chip and the third conductive member of the third chip. The first chip is provided between the first terminal and the second terminal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2018-000065, filed on Jan. 4, 2018,Japanese Patent Application No. 2018-109356, filed on Jun. 7, 2018, andJapanese Patent Application No. 2018-128380, filed on Jul. 5, 2018; theentire contents of all of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to an electronic device.

BACKGROUND

A fan-out interconnect layer performs the role of connecting signallines between multiple chips and the role of power supply to the chips.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic cross-sectional view illustrating an electronicdevice according to a first embodiment, FIGS. 1B and 1C are schematicenlarged cross-sectional views of a first chip of the electronic deviceaccording to the first embodiment, and FIG. 1D is a schematic viewshowing a connectional relationship of the first chip, a second chip,and a third chip of the electronic device according to the firstembodiment;

FIG. 2A is a schematic plan view showing an arrangement example of thefirst chip, the second chip, and the third chip of the electronic deviceaccording to the first embodiment, and FIG. 2B is a schematic plan viewof the second chip, the third chip, and a resin portion of theelectronic device according to the first embodiment;

FIG. 3A to FIG. 6E are schematic cross-sectional views showing anexample of a method for manufacturing the electronic device according tothe first embodiment;

FIG. 7 is a schematic cross-sectional view illustrating an electronicdevice according to a second embodiment;

FIGS. 8A and 8B are schematic views showing a connectional relationshipof a first chip, a second chip, and a third chip of the electronicdevice according to the second embodiment;

FIG. 9 is a schematic view showing a connectional relationship of afirst chip, a second chip, and a third chip of an electronic deviceaccording to a third embodiment;

FIG. 10 is a schematic cross-sectional view illustrating an electronicdevice according to a fourth embodiment;

FIG. 11A is a schematic cross-sectional view illustrating an electronicdevice according to a fifth embodiment, FIG. 11B is a schematiccross-sectional view illustrating another example of the electronicdevice according to the fifth embodiment;

FIG. 12 is a schematic plan view showing an arrangement example of afirst chip and a second chip of the electronic device according to thefifth embodiment;

FIG. 13 is a schematic cross-sectional view illustrating an electronicdevice according to a sixth embodiment;

FIG. 14 is a schematic view showing a connectional relationship of afirst chip and a second chip of the electronic device according to thesixth embodiment;

FIG. 15 is a schematic plan view showing a composition of the first chipof the electronic device according to the sixth embodiment;

FIG. 16A is a schematic view showing a connectional relationship of afirst chip, a second chip, and a third chip of an electronic deviceaccording to a seventh embodiment, and FIG. 16B is a schematic viewshowing a connectional relationship of a first chip and a second chip anelectronic device according to an eighth embodiment;

FIG. 17 is a schematic cross-sectional view of an electronic device of amodification of the electronic device shown in FIG. 1A;

FIG. 18 is a schematic cross-sectional view of an electronic device of amodification of the electronic device shown in FIG. 7;

FIG. 19 is a schematic cross-sectional view of an electronic device of amodification of the electronic device shown in FIG. 10;

FIG. 20 is a schematic cross-sectional view of an electronic device of amodification of the electronic device shown in FIG. 13;

FIG. 21 is a schematic cross-sectional view of an electronic deviceaccording to an ninth embodiment;

FIG. 22 is a schematic view showing an arrangement and connections ofthe first chip, the second chip, the third chip, and the interconnectlayer according to the second embodiment;

FIG. 23 is a schematic plan view of the electronic device shown in FIG.22;

FIG. 24 is a schematic view in which positions of the second chips andpositions of the third chips of FIG. 23 are interchanged;

FIG. 25 is a schematic plan view showing an application example of theelectronic device of the second embodiment to a neural network;

FIG. 26 is a descriptive view of a neural network;

FIG. 27 is a schematic plan view showing an application example of theelectronic device of the second embodiment to a neural network;

FIG. 28 is a schematic plan view showing a full grid tile structure ofthe first chips, the second chips, and the third chips of the electronicdevice according to the second embodiment;

FIG. 29 is a schematic plan view showing an application example of theembodiment shown in FIG. 28 to a neural network; and

FIG. 30 is a schematic cross-sectional view of an example of the thirdchip according to the embodiments.

DETAILED DESCRIPTION

According to one embodiment, an electronic device includes a first chip,a second chip, a third chip, a first terminal, a second terminal, and aninterconnect layer. The first chip includes a first conductive member, afirst region, and a second region. The second chip includes a secondconductive member, a third region, and a fourth region. The third chipincludes a third conductive member, a fifth region, and a sixth region.The interconnect layer is provided between the first region of the firstchip and the third region of the second chip, between the second regionof the first chip and the fifth region of the third chip, between thefirst terminal and the fourth region of the second chip, and between thesecond terminal and the sixth region of the third chip. The interconnectlayer includes a fourth conductive member and a fifth conductive member.The fourth conductive member is provided between the first region of thefirst chip and the third region of the second chip. The fourthconductive member connects the first conductive member of the first chipand the second conductive member of the second chip. The fifthconductive member is provided between the second region of the firstchip and the fifth region of the third chip. The fifth conductive memberconnects the first conductive member of the first chip and the thirdconductive member of the third chip. The first chip is provided betweenthe first terminal and the second terminal.

Various embodiments will be described hereinafter with reference to theaccompanying drawings.

The drawings are schematic and conceptual; and the relationships betweenthe thickness and width of portions, the proportions of sizes amongportions, etc., are not necessarily the same as the actual valuesthereof. Further, the dimensions and proportions may be illustrateddifferently among drawings, even for identical portions.

In the specification and drawings, components similar to those describedor illustrated in a drawing thereinabove are marked with like referencenumerals, and a detailed description is omitted as appropriate.

In the following embodiments, an electronic device is, for example, asemiconductor device.

First Embodiment

FIG. 1A is a schematic cross-sectional view illustrating an electronicdevice 1 according to a first embodiment.

FIGS. 1B and 1C are schematic enlarged cross-sectional views of a firstchip 10 of the electronic device 1.

FIG. 1D is a schematic view showing the connectional relationship of thefirst chip 10, a second chip 20, and a third chip 30 of the electronicdevice 1.

FIG. 2A is a schematic plan view showing an arrangement example of thefirst chip 10, the second chip 20, and the third chip 30 of theelectronic device 1.

FIG. 2B is a schematic plan view of the second chip 20, the third chip30, and a resin portion 51 of the electronic device 1.

As shown in FIG. 1A, the electronic device 1 according to the firstembodiment includes an interconnect layer 40, the first chip 10, thesecond chip 20, the third chip 30, the resin portion 51, multiple firstterminals 81, and multiple second terminals 82.

The first chip 10 includes a first region 10 a and a second region 10 b.The second chip 20 includes a third region 20 a and a fourth region 20b. The third chip 30 includes a fifth region 30 a and a sixth region 30b.

The direction from the first region 10 a of the first chip 10 toward thethird region 20 a of the second chip 20 is aligned with a firstdirection. The direction from the second region 10 b of the first chip10 toward the fifth region 30 a of the third chip 30 is aligned with thefirst direction.

The first direction is taken as a Z-axis direction. One directionperpendicular to the Z-axis direction is taken as an X-axis direction. Adirection perpendicular to the Z-axis direction and the X-axis directionis taken as a Y-axis direction.

For example, the interconnect layer 40 is aligned with the X-Y plane.

A second direction from the second chip 20 toward the third chip 30crosses the first direction. In the example, the second direction isaligned with the X-axis direction.

The direction from the first region 10 a of the first chip 10 toward thefourth region 20 b of the second chip 20 crosses the first direction andthe second direction. The direction from the second region 10 b of thefirst chip 10 toward the sixth region 30 b of the third chip 30 crossesthe first direction and the second direction.

The interconnect layer 40 is provided between the first region 10 a ofthe first chip 10 and the third region 20 a of the second chip 20,between the second region 10 b of the first chip 10 and the fifth region30 a of the third chip 30, between the fourth region 20 b of the secondchip 20 and the first terminals 81, and between the sixth region 30 b ofthe third chip 30 and the second terminals 82.

As shown in FIG. 1B, the first chip 10 includes a substrate 12 and aninterconnect layer 14. The thickness along the Z-axis direction of thesubstrate 12 is thicker than the thickness along the Z-axis direction ofthe interconnect layer 14.

The substrate 12 is, for example, a silicon substrate or a glasssubstrate. The interconnect layer 14 is, for example, an interconnectlayer formed by a damascene process and/or a semi-additive process. Theinterconnect layer 14 includes an insulating layer 13 and a firstconductive member 11. A high-resistance silicon substrate may be used asthe substrate 12 in the case where the first chip 10 is a bridge chipthat does not include an element and simply functions as only aninterconnect. The specific resistance of the high-resistance siliconsubstrate is, for example, 10 Ωcm or more.

The first conductive member 11 is, for example, a metal member. Thefirst conductive member 11 includes multiple electrode terminals 11 a,and a conductive layer 11 b connected to the electrode terminals 11 a.The conductive layer 11 b is provided between the substrate 12 and theelectrode terminals 11 a.

Or, as shown in FIG. 1C, the first chip 10 includes only theinterconnect layer 14 including the first conductive member 11 and doesnot include the substrate 12. The substrate 12 can be removed afterforming the interconnect layer 14 in the substrate 12.

As shown in FIG. 1A, an insulating portion 55 is provided between thefirst chip 10 and the interconnect layer 40. For example, the insulatingportion 55 is made of a resin material or an inorganic material. Theinsulating portion 55 covers the first conductive member 11. Forexample, the insulating portion 55 can be injected after connecting thefirst conductive member 11 to the interconnect layer 40. Or, a formationmethod may be used in which the insulating portion 55 is pre-formed in aregion including the periphery of the first conductive member 11; andthe insulating portion 55 is connected to the interconnect layer 40simultaneously with the first conductive member 11.

The second chip 20 includes a second conductive member 21 as shown inFIG. 1A. The second conductive member 21 is, for example, a metalmember. The second conductive member 21 includes a first signal terminal21 a, a first power supply terminal 21 b, and a conductive layer (notillustrated) connected to the first signal terminal 21 a and the firstpower supply terminal 21 b. The second chip 20 includes, for example, alogic element. For example, the logic element is used mainly forfunctions relating to the calculation/control of information.

The third chip 30 includes a third conductive member 31 as shown in FIG.1A. The third conductive member 31 is, for example, a metal member. Thethird conductive member 31 includes a second signal terminal 31 a, asecond power supply terminal 31 b, and a conductive layer (notillustrated) connected to the second signal terminal 31 a and the secondpower supply terminal 31 b. The third chip 30 includes, for example, amemory element. For example, the memory element is used mainly forfunctions relating to the storage of information.

The interconnect layer 40 includes an insulating layer 45, a fourthconductive member 41, a fifth conductive member 42, a sixth conductivemember 43, and a seventh conductive member 44.

The insulating layer 45 is, for example, a resin layer. The insulatinglayer 45 is provided between the fourth conductive member 41, the fifthconductive member 42, the sixth conductive member 43, and the seventhconductive member 44. The insulating layer 45 insulatively separatesbetween the fourth conductive member 41, the fifth conductive member 42,the sixth conductive member 43, and the seventh conductive member 44.The insulating layer 45 may be a layer of an inorganic insulatingmaterial.

The fourth conductive member 41 is provided between the first region 10a of the first chip 10 and the third region 20 a of the second chip 20and connects the first conductive member 11 of the first chip 10 and thefirst signal terminal 21 a of the second chip 20. The fourth conductivemember 41 extends along the Z-axis direction and is, for example, ametal via. Many inter-chip interconnect connections are possible byarranging multiple fourth conductive members 41 in an arrayconfiguration in the X-Y plane.

The fifth conductive member 42 is provided between the second region 10b of the first chip 10 and the fifth region 30 a of the third chip 30and connects the first conductive member 11 of the first chip 10 and thesecond signal terminal 31 a of the third chip 30. The fifth conductivemember 42 extends along the Z-axis direction and is, for example, ametal via. Many inter-chip interconnect connections are possible byarranging multiple fifth conductive members 42 in an array configurationin the X-Y plane.

The sixth conductive member 43 is provided between the fourth region 20b of the second chip 20 and the first terminal 81 and connects the firstpower supply terminal 21 b of the second chip 20 and the first terminal81.

The seventh conductive member 44 is provided between the sixth region 30b of the third chip 30 and the second terminal 82 and connects thesecond power supply terminal 31 b of the third chip 30 and the secondterminal 82.

The sixth conductive member 43 and the seventh conductive member 44 are,for example, metal interconnects. The first terminals 81 and the secondterminals 82 are external terminals connecting the electronic device 1to an external circuit. The first terminals 81 and the second terminals82 are, for example, solder balls. The first terminals 81 and the secondterminals 82 may be metal pads or metal bumps.

The first chip 10 is provided between the first terminals 81 and thesecond terminals 82. The direction from the first terminals 81 towardthe first chip 10 is aligned with the X-axis direction. The directionfrom the second terminals 82 toward the first chip 10 is aligned withthe X-axis direction.

The resin portion 51 covers at least a portion of the side surfaces ofthe second chip 20 and the third chip 30. The side surfaces cross theX-Y plane. Although an embodiment is shown in the example shown in FIG.1A in which the surfaces of the second chip 20 and the third chip 30opposite to the interconnect layer 40 also are covered with the resinportion 51, the exposure from the resin portion 51 of the surfacesopposite to the interconnect layer 40 is arbitrary.

As shown in FIG. 1A, the resin portion 51 includes a first resin region51 a, a second resin region 51 b, and a third resin region 51 c. Asshown in FIG. 2B, the resin portion 51 further includes a fourth resinregion 51 d and a fifth resin region 51 e. The first to fifth resinregions 51 a to 51 e are continuous with each other.

Although a configuration is used in the example shown in FIG. 1A inwhich the resin portion 51 is disposed also at the peripheral portion ofthe second conductive member 21 and the peripheral portion of the thirdconductive member 31, the resin portion 51 may not be disposed at theperipheral portion of the second conductive member 21 and the peripheralportion of the third conductive member 31; for example, a differentinsulating material may be disposed at the peripheral portion of thesecond conductive member 21 and the peripheral portion of the thirdconductive member 31.

The second chip 20 is provided between the first resin region 51 a andthe third resin region 51 c. The direction from the first resin region51 a toward the third resin region 51 c is aligned with the X-axisdirection. The third chip 30 is provided between the third resin region51 c and the second resin region 51 b. The third resin region 51 c isprovided between the second chip 20 and the third chip 30. The directionfrom the third resin region 51 c toward the second resin region 51 b isaligned with the X-axis direction.

The second chip 20 is provided between the fourth resin region 51 d andthe fifth resin region 51 e. The third chip 30 is provided between thefourth resin region 51 d and the fifth resin region 51 e. The directionfrom the fourth resin region 51 d toward the fifth resin region 51 e isaligned with the Y-axis direction.

The interconnect layer 40 is provided also between the first resinregion 51 a and the first terminals 81 and between the second resinregion 51 b and the second terminals 82.

The electronic device 1 according to the first embodiment furtherincludes a fourth chip 70, an eighth conductive member 52, a ninthconductive member 53, and a semiconductor package device 60.

The fourth chip 70 includes, for example, an IPD (Integrated PassiveDevice) or a passive element. The passive element includes, for example,a discrete component such as a capacitor, an inductor, a resistanceelement, etc. For example, the fourth chip 70 is connected to the sixthconductive member 43.

The interconnect layer 40 is provided between the fourth chip 70 and thefourth region 20 b of the second chip 20. The direction from the fourthchip 70 toward the second chip 20 is aligned with the Z-axis direction.

The fourth chip 70 is provided between the first terminals 81 and thefirst chip 10. The direction from the fourth chip 70 toward the firstchip 10 is aligned with the X-axis direction.

The eighth conductive member 52 is, for example, a metal via having acolumnar configuration extending in the Z-axis direction. The ninthconductive member 53 is, for example, a solder ball.

The semiconductor package device 60 includes, for example, a DRAM(Dynamic Random Access Memory) element or NVM (Non Volatile Memory)typified by flash memory, etc.

The eighth conductive member 52, the ninth conductive member 53, thesecond chip 20, the third chip 30, and the resin portion 51 are providedbetween the semiconductor package device 60 and the interconnect layer40.

The ninth conductive member 53 is provided between the eighth conductivemember 52 and the semiconductor package device 60 and is connected tothe eighth conductive member 52 and the semiconductor package device 60.

The eighth conductive member 52 is provided between the interconnectlayer 40 and the ninth conductive member 53. The eighth conductivemember 52 is connected to the ninth conductive member 53 and to thesixth conductive member 43 and the seventh conductive member 44 of theinterconnect layer 40.

As shown in FIG. 1A and FIG. 2A, the length along the X-axis directionof the first chip 10 is shorter than the length along the X-axisdirection of the second chip 20 and the length along the X-axisdirection of the third chip 30.

The first conductive member 11 of the first chip 10 is electricallyconnected to the first signal terminal 21 a of the second chip 20 viathe fourth conductive member 41. The first conductive member 11 of thefirst chip 10 is electrically connected to the second signal terminal 31a of the third chip 30 via the fifth conductive member 42. Accordingly,the first signal terminal 21 a of the second chip 20 is electricallyconnected to the second signal terminal 31 a of the third chip 30 viathe fourth conductive member 41, the first conductive member 11 of thefirst chip 10, and the fifth conductive member 42.

A power supply is supplied to the first power supply terminal 21 b ofthe second chip 20 via the first terminal 81 and the sixth conductivemember 43 and supplied to the second power supply terminal 31 b of thethird chip 30 via the second terminal 82 and the seventh conductivemember 44.

The fourth conductive member 41 and the sixth conductive member 43 arenot connected to each other; and the fifth conductive member 42 and theseventh conductive member 44 are not connected to each other.Accordingly, the power supply is not supplied to the first chip 10; andthe first chip 10 functions simply as an interconnect member connectingthe second chip 20 and the third chip 30. The first chip 10 does notinclude a passive element or an active element such as a transistor,etc.

According to the electronic device 1 according to the first embodiment,the second chip 20 and the third chip 30 are connected to each other viathe first chip 10. For example, a high-density fine interconnect can beformed in the first chip 10 at a low cost using a wafer process. It isunnecessary to form a high-density fine interconnect for the inter-chipconnection in the interconnect layer 40 to which the second chip 20 andthe third chip 30 are mounted; and the interconnect can be only aninterconnect having a rough line-and-space formable at the panel levelhaving a large surface area. This not only makes a cost reductionpossible but also reduces the source impedance to the second chip 20 andthe third chip 30 via the sixth conductive member 43 and the seventhconductive member 44 and contributes to the electrical power supplyperformance improvement.

Also, the first chip 10 can have a structure of only an interconnectthat does not include an active element, a passive element, etc.; andthe cost can be reduced drastically. Further, the chip size of the firstchip 10 can be downsized by the amount that an element is not included;and a wide region where the first terminals 81 and the second terminals82 are arranged can be ensured. This makes it possible to reduce thedistance between the first power supply terminal 21 b of the second chip20 and the first terminal 81 and the distance between the second powersupply terminal 31 b of the third chip 30 and the second terminal 82;and the source impedances of the second chip 20 and the third chip 30can be reduced. The decrease of the source impedance deters thefluctuation of the power supply voltage and makes stable operationspossible.

The third chip 30 includes, for example, cache memory as a memoryelement. The semiconductor package device 60 may include, for example,DRAM as main memory having a larger memory capacity than the cachememory, or NVM (Non Volatile Memory) typified by flash memory or thelike as storage memory. The second chip 20 can have a function ofcontrolling the third chip 30 and the semiconductor package device 60.

According to such an embodiment, compared to a configuration in whichthe cache memory is internally integrated in the second chip 20, forexample, cache memory that has a large capacity can be embedded as asystem inside one package; the improvement of the system performance isrealized; and a cost reduction of the inter-chip connection interconnectand high electrical power supply performance to each chip can berealized.

FIG. 3A to FIG. 6D are schematic cross-sectional views showing anexample of the method for manufacturing the electronic device 1according to the first embodiment.

As shown in FIG. 3A, the interconnect layer 40 is formed on a supporter100. The interconnect layer 40 includes the insulating layer 45, thefourth conductive member 41, the fifth conductive member 42, the sixthconductive member 43, and the seventh conductive member 44 describedabove.

For example, FIGS. 6A to 6D show processes of forming the fourthconductive member 41. The supporter 100 is not illustrated in FIGS. 6Bto 6D.

Although a release layer also may be disposed between the interconnectlayer 40 and the supporter 100, such a release layer is not illustrated.The release layer is a laminar material for providing the function ofseparating the interconnect layer 40 and the supporter 100 by applyingmechanical stress and/or optical energy (laser irradiation, etc.).

After forming a pad 92 on the supporter 100, an insulating layer 91 thatcovers the pad 92 is formed. A hole 91 a that reaches the pad 92 isformed in the insulating layer 91.

As shown in FIG. 6B, a via 93 is formed inside the hole 91 a. The endportion of the via 93 is formed also on the insulating layer 91. Aconductive layer 94 that is included in the sixth conductive member 43and a conductive layer 95 that is included in the seventh conductivemember 44 are formed on the insulating layer 91 simultaneously with thevia 93.

As shown in FIG. 6C, an insulating layer 96 is further stacked with theinsulating layer 91. A hole 96 a that reaches the end portion of the via93 is formed in the insulating layer 96.

As shown in FIG. 6D, a via 97 is formed inside the hole 96 a.Subsequently, an insulating layer may be formed; a hole may be formed inthe insulating layer; and a via may be formed inside the hole.

The fourth conductive member 41 that has a stacked via structureincluding the multiple vias 93 and 97 connected to each other in theZ-axis direction is formed by multiply repeating the process of formingthe insulating layer, the process of forming the hole in the insulatinglayer, and the process of forming the via inside the hole. The fifthconductive member 42 that has the same stacked via structure also isformed similarly to the fourth conductive member 41. The via 93 and thevia 97 are not limited to being arranged in linear configurations alongthe Z-axis direction; and the positions of the via 93 and the via 97 maybe shifted in the X-axis direction (or the Y-axis direction) as shown inFIG. 6E.

After forming the interconnect layer 40, the eighth conductive member 52is fixed to the interconnect layer 40 as shown in FIG. 3B. Further, asshown in FIG. 4A, the second chip 20 and the third chip 30 are fixed tothe interconnect layer 40. The second chip 20 and the third chip 30 maybe fixed to the interconnect layer 40 before the eighth conductivemember 52.

The eighth conductive member 52, the second chip 20, and the third chip30 are covered with the resin portion 51 as shown in FIG. 4B. The resinportion 51 is stacked with the interconnect layer 40.

The supporter 100 is removed after forming the resin portion 51. Thesupporter 100 may be removed by utilizing the function provided by therelease layer described above; or the supporter 100 may be removed by amethod such as polishing, etching, etc. By these processes, the surfaceof the interconnect layer 40 that opposed the supporter 100 is exposedas shown in FIG. 5A.

The first chip 10 and the fourth chip 70 are fixed to the exposedsurface of the interconnect layer 40 as shown in FIG. 5B. After fixingthe first chip 10 to the interconnect layer 40, the substrate 12 of thefirst chip 10 shown in FIG. 16 may be removed.

Subsequently, the first terminals 81 and the second terminals 82 shownin FIG. 1A are fixed to the interconnect layer 40; further, thesemiconductor package device 60 is stacked. The order of stacking thesemiconductor package device 60 may be after the first terminals 81 andthe second terminals 82 are fixed.

Second Embodiment

FIG. 7 is a schematic cross-sectional view illustrating an electronicdevice 2 according to a second embodiment.

FIG. 8A is a schematic view showing the connectional relationshipbetween a first chip 110, the second chip 20, and the third chip 30 ofthe electronic device 2. FIG. 8B is a schematic view in a planeillustrating the connectional relationship between the first chip 110,the second chip 20, and the third chip 30. As shown in FIG. 7, theelectronic device 2 according to the second embodiment includes theinterconnect layer 40, the first chip 110, the second chip 20, the thirdchip 30, the resin portion 51, the multiple first terminals 81, and themultiple second terminals 82.

The first chip 110 includes a first conductive member 111, a firstregion 110 a, and a second region 110 b. The direction from the firstregion 110 a of the first chip 110 toward the third region 20 a of thesecond chip 20 is aligned with the first direction. The direction fromthe second region 110 b of the first chip 110 toward the fifth region 30a of the third chip 30 is aligned with the first direction.

The first region 110 a of the first chip 110 faces the third region 20 aof the second chip 20 and is a connection region connected to the thirdregion 20 a of the second chip 20. The third region 20 a of the secondchip 20 faces the first region 110 a of the first chip 110 and is theregion of the connection to the first region 110 a of the first chip110. The second region 110 b of the first chip 110 faces the fifthregion 30 a of the third chip 30 and is a connection region connected tothe fifth region 30 a of the third chip 30. The fifth region 30 a of thethird chip 30 faces the second region 110 b of the first chip 110 and isa connection region connected to the second region 110 b of the firstchip 110.

The direction from the first region 110 a of the first chip 110 towardthe fourth region 20 b of the second chip 20 crosses the first directionand the second direction. The direction from the second region 110 b ofthe first chip 110 toward the sixth region 30 b of the third chip 30crosses the first direction and the second direction.

The interconnect layer 40 is provided between the first region 110 a ofthe first chip 110 and the third region 20 a of the second chip 20,between the second region 110 b of the first chip 110 and the fifthregion 30 a of the third chip 30, between the fourth region 20 b of thesecond chip 20 and the first terminals 81, and between the sixth region30 b of the third chip 30 and the second terminals 82.

The fourth conductive member 41 of the interconnect layer 40 is providedbetween the first region 110 a of the first chip 110 and the thirdregion 20 a of the second chip 20 and connects the first conductivemember 111 of the first chip 110 and the signal terminal 21 a of thesecond chip 20. Many inter-chip interconnect connections are possible byarranging multiple fourth conductive members 41 in an arrayconfiguration in the X-Y plane.

The fifth conductive member 42 of the interconnect layer 40 is providedbetween the second region 110 b of the first chip 110 and the fifthregion 30 a of the third chip 30 and connects the first conductivemember 111 of the first chip 110 and the fourth signal terminal 31 a ofthe third chip 30. Many inter-chip interconnect connections are possibleby arranging multiple fifth conductive members 42 in an arrayconfiguration in the X-Y plane.

The first chip 110 is provided between the first terminals 81 and thesecond terminals 82. The direction from the first terminals 81 towardthe first chip 110 is aligned with the X-axis direction. The directionfrom the second terminals 82 toward the first chip 110 is aligned withthe X-axis direction.

The length along the X-axis direction of the first chip 110 is shorterthan the length along the X-axis direction of the second chip 20 and thelength along the X-axis direction of the third chip 30.

Similarly to the first chip 10 of the first embodiment recited above,the first chip 110 includes the first conductive member 111 connectingbetween the second chip 20 and the third chip 30. As shown in FIG. 8A,the first chip 110 may further include a first memory element 113. Thefirst memory element 113 is, for example, cache memory.

The third chip 30 includes a second memory element 115. The secondmemory element 115 is, for example, main memory and may be DRAM. In thecase where the first chip 110 includes a first memory element 113, thememory capacity of the second memory element 115 is larger than thememory capacity of the first memory element 113.

An example is shown in FIG. 7 in which multiple third chips 30 arestacked in the Z-axis direction. The first memory element 113 has afaster operation speed than the second memory element 115. Variousmethods may be used as the connection method between the multiple thirdchips 30; and the connection method may be, for example, a TSV (ThroughSilicon Via) or a metal wire connection. Because the third chip 30 thatincludes the second memory element 115 is provided on the side oppositeto the mounting surface of the electronic device 2 for the board, thestacking of the multiple third chips 30 is easy; and it is easy toincrease the capacity of the second memory element 115.

The second chip 20 includes, for example, a logic element and controlsthe first memory element 113 of the first chip 110 and the second memoryelement 115 of the third chip 30. Or, the logic element of the secondchip 20 may control only the second memory element 115 of the third chip30. In the specification, “control” includes the mutual data transferbetween the logic element and the memory element, the control of themutual data transfer, the data movement inside the memory element, andthe control of the data movement.

As shown in FIG. 8A, the first conductive member 111 of the first chip110 includes multiple interconnects 112 connecting the second chip 20and the third chip 30. The interconnects 112 are, for example, metalinterconnects. Or, the interconnects 112 may be optical interconnects(or optical waveguides). The interconnects 112 function as buses for thedata transfer from the second chip 20 to the third chip 30.

As shown in FIG. 8A and FIG. 8B, the second chip 20 includes multiplesecond signal terminals 21 aa and multiple third signal terminals 21 ab.The second signal terminals 21 aa and the multiple third signalterminals 21 ab are provided in the third region 20 a of the second chip20.

The first chip 110 includes multiple first signal terminals 113 aelectrically connected to the first memory element 113. The first signalterminals 113 a are provided in the first region 110 a of the first chip110.

The fourth conductive member 41 of the interconnect layer 40 includesmultiple metal vias 41 a and multiple metal vias 41 b. The metal vias 41a connects the second signal terminals 21 aa of the second chip 20 andthe first signal terminals 113 a of the first chip 110. The metal vias41 b connects the third signal terminals 21 ab of the second chip 20 andthe interconnects 112.

The third chip 30 includes multiple fourth signal terminals 31 aelectrically connected to the second memory element 115. The fourthsignal terminals 31 a are provided in the fifth region 30 a of the thirdchip 30. The fourth signal terminals 31 a are connected to theinterconnects 112 of the first chip 110.

The interconnects 112 of the first chip 110 connect the third signalterminals 21 ab of the second chip 20 and the fourth signal terminals 31a of the third chip 30. The interconnects 112 are not connected to thesixth conductive member 43 and the seventh conductive member 44 of theinterconnect layer 40 which are interconnects for connecting the firstchip 110, the second chip 20, and the third chip 30 to the outside. Forexample, the interconnects of the interconnect layer 40 also are metalinterconnects. Or, the interconnects of the interconnect layer 40 may beoptical interconnects (or optical waveguides).

The connections between the second chip 20 and the first memory element113 are via connections provided by the metal vias 41 a without goingthrough the interconnects 112.

A power supply is supplied to the first chip 110 including the firstmemory element 113. The first conductive member 111 of the first chip110 shown in FIG. 7 is electrically connected to the first terminals 81via the sixth conductive member 43. Or, the first conductive member 111of the first chip 110 is electrically connected to the second terminals82 via the seventh conductive member 44. The power supply also may beperformed to the first chip 110 via the second chip 20 or the third chip30.

The interconnects 112 that are provided in the first chip 110 areso-called on-chip interconnects formed by a semiconductor wafer process.Conversely, the sixth conductive member 43 and the seventh conductivemember 44 which are interconnects of the interconnect layer 40 can berough interconnects formed at the panel level which is larger than asemiconductor wafer. In other words, the minimum spacing of theinterconnects 112 of the first chip 110 is smaller than the minimumspacing of the interconnects of the interconnect layer 40.

In the electronic device 2 according to the second embodiment as well,the second chip 20 and the third chip 30 are connected to each other viathe first chip 110. For example, a high-density fine interconnect can beformed in the first chip 110 at a low cost using a wafer process. It isunnecessary to form a high-density fine interconnect for the inter-chipconnection in the interconnect layer 40 to which the second chip 20 andthe third chip 30 are mounted; and the interconnect can be only aninterconnect having a rough line-and-space formable at the panel level.This makes a cost reduction possible.

The first chip 110 performs mainly the function of the inter-chipinterconnect; and the chip size of the first chip 110 can be small. Awide region where the first terminals 81 and the second terminals 82 aredisposed can be ensured by this amount. This makes it possible to reducethe distance between the first power supply terminal 21 b of the secondchip 20 and the first terminal 81 and the distance between the secondpower supply terminal 31 b of the third chip 30 and the second terminal82; and the source impedances of the second chip 20 and the third chip30 can be reduced. The decrease of the source impedance deters thefluctuation of the power supply voltage and makes stable operationspossible.

Also, according to the second embodiment, the first chip 110 not onlymay perform the inter-chip connection but also may have a memoryfunction. According to such a second embodiment, the improvement of thesystem performance and the higher capacity by the increased layers ofthe memory layer structure are possible.

Third Embodiment

FIG. 9 is a schematic view showing the connectional relationship betweena first chip 110′, the second chip 20, and the third chip 30 of anelectronic device according to a third embodiment.

The electronic device according to the third embodiment has thestructure of the electronic device 2 according to the second embodimentshown in FIG. 7 in which the first chip 110 is replaced with the firstchip 110′. In other words, the first chip 110′ also includes theinterconnects 112, the first region 110 a, and the second region 110 bsimilar to those of the first chip 110.

As shown in FIG. 9, the first chip 110′ further includes the firstmemory element 113 and a controller 114. The first memory element 113is, for example, cache memory. The first chip 110′ includes multiplefirst signal terminals 113 a electrically connected to the first memoryelement 113.

The third chip 30 includes the second memory element 115, the multiplefourth signal terminals 31 a, and the multiple sixth signal terminals 31b. The multiple fourth signal terminals 31 a and the multiple sixthsignal terminals 31 b are connected to the second memory element 115.

The second chip 20 includes the multiple second signal terminals 21 aa,the multiple third signal terminals 21 ab, and multiple fifth signalterminals 21 ac.

The controller 114 of the first chip 110′ is connected to the sixthsignal terminals 31 b of the third chip 30 via multiple metal vias 42.The controller 114 controls the second memory element 115 of the thirdchip 30. In other words, the first chip 110′ has the function ofcontrolling the second memory element 115 having the large capacity.

The controller 114 of the first chip 110′ is connected to the firstmemory element 113 via multiple interconnects 116 inside the first chip110′ and controls the first memory element 113.

Also, the controller 114 of the first chip 110′ is connected to thefifth signal terminals 21 ac of the second chip 20 via interconnects 117provided in the interconnect layer 40.

A power supply is supplied to the first chip 110′ via the firstterminals 81 and the sixth conductive member 43. Or, the power supply issupplied to the first chip 110′ via the second terminals 82 and theseventh conductive member 44.

According to the configuration shown in FIG. 9, the controller 114 ofthe first chip 110′ can control both the second memory element 115 ofthe third chip 30 and the first memory element 113 of the first chip110′. This makes it possible to optimize the data placement of thememory layer structure without consuming the information processing timeand the operating energy accompanying the control of both the firstmemory element 113 and the second memory element 115 of the logicelement of the second chip 20. For example, in the case where the firstmemory element 113 is cache memory, the appropriate movement of the datanecessary for the logic element of the second chip 20 from the secondmemory element 115 of the third chip 30 to the first memory element 113is realizable without relying on the control of the second chip 20.

Fourth Embodiment

FIG. 10 is a schematic cross-sectional view illustrating an electronicdevice 3 according to a fourth embodiment.

The electronic device 3 according to the fourth embodiment includes aninterconnect layer 240, a first chip 210, a second chip 220, a thirdchip 230, the resin portion 51, the multiple first terminals 81, and themultiple second terminals 82.

The first chip 210 includes a first optical element 211, a secondoptical element 212, and an optical waveguide 213. The first opticalelement 211 includes a first electrode terminal 211 a; and the secondoptical element 212 includes a second electrode terminal 212 a.

The first optical element 211 is, for example, a light-emitting elementor a light receiving element. The second optical element 212 is, forexample, a light-emitting element or a light receiving element. Theoptical waveguide 213 is provided between the first optical element 211and the second optical element 212. The first optical element 211 andthe second optical element 212 are optically coupled to the opticalwaveguide 213.

The second chip 220 includes a first region 220 a and a second region220 b. The third chip 230 includes a third region 230 a and a fourthregion 230 b.

The direction from the first optical element 211 of the first chip 210toward the first region 220 a of the second chip 20 is aligned with thefirst direction. The direction from the second optical element 212 ofthe first chip 210 toward the third region 230 a of the third chip 30 isaligned with the first direction. The second direction from the secondchip 220 toward the third chip 230 crosses the first direction. In theexample, the second direction is aligned with the X-axis direction. Thedirection from the first optical element 211 toward the second opticalelement 212 is aligned with the second direction.

The direction from the first optical element 211 of the first chip 210toward the second region 220 b of the second chip 220 crosses the firstdirection and the second direction. The direction from the secondoptical element 212 of the first chip 210 toward the fourth region 230 bof the third chip 230 crosses the first direction and the seconddirection.

The interconnect layer 240 is provided between the first optical element211 of the first chip 210 and the first region 220 a of the second chip220, between the second optical element 212 of the first chip 210 andthe third region 230 a of the third chip 230, between the second region220 b of the second chip 220 and the first terminals 81, and between thefourth region 230 b of the third chip 230 and the second terminals 82.

An insulating portion 255 is provided between the first chip 210 and theinterconnect layer 240. For example, the insulating portion 255 is madeof a resin material or an inorganic material. The insulating portion 255covers the first electrode terminal 211 a of the first optical element211 and the second electrode terminal 212 a of the second opticalelement 212. For example, the insulating portion 255 can be injectedafter connecting the first electrode terminal 211 a and the secondelectrode terminal 212 a to the interconnect layer 240. Or, a formationmethod may be used in which the insulating portion 255 is pre-formed ina region including the peripheries of the first electrode terminal 211 aand the second electrode terminal 212 a; and the insulating portion 255is connected to the interconnect layer 240 simultaneously with the firstelectrode terminal 211 a and the second electrode terminal 212 a.

The second chip 220 includes a first conductive member 221. The firstconductive member 221 is, for example, a metal member. The firstconductive member 221 includes a first signal terminal 221 a, a firstpower supply terminal 221 b, and a conductive layer (not illustrated)connected to the first signal terminal 221 a and the first power supplyterminal 221 b. The second chip 220 includes, for example, a logicelement.

The third chip 230 includes a second conductive member 231. The secondconductive member 231 is, for example, a metal member. The secondconductive member 231 includes a second signal terminal 231 a, a secondpower supply terminal 231 b, and a conductive layer (not illustrated)connected to the second signal terminal 231 a and the second powersupply terminal 231 b. The third chip 230 includes, for example, amemory element or a logic element.

The interconnect layer 240 includes the insulating layer 45, a thirdconductive member 241, a fourth conductive member 242, a fifthconductive member 243, and a sixth conductive member 244.

The insulating layer 45 is, for example, a resin layer. The insulatinglayer 45 is provided between the third conductive member 241, the fourthconductive member 242, the fifth conductive member 243, and the sixthconductive member 244.

The third conductive member 241 is provided between the first opticalelement 211 of the first chip 210 and the first region 220 a of thesecond chip 220 and electrically connects the first electrode terminal211 a of the first optical element 211 and the first signal terminal 221a of the second chip 220. The third conductive member 241 is, forexample, a metal via extending along the Z-axis direction. Manyinter-chip interconnect connections are possible by arranging multiplethird conductive members 241 in an array configuration in the X-Y plane.

The fourth conductive member 242 is provided between the second opticalelement 212 of the first chip 210 and the third region 230 a of thethird chip 230 and electrically connects the second electrode terminal212 a of the second optical element 212 and the second signal terminal231 a of the third chip 230. The fourth conductive member 242 extendsalong the Z-axis direction and is, for example, a metal via. Manyinter-chip interconnect connections are possible by arranging multiplefourth conductive members 242 in an array configuration in the X-Yplane.

The fifth conductive member 243 is provided between the second region220 b of the second chip 220 and the first terminals 81 and connects thefirst power supply terminal 221 b of the second chip 220 and the firstterminals 81.

The sixth conductive member 244 is provided between the fourth region230 b of the third chip 230 and the second terminals 82 and connects thesecond power supply terminal 231 b of the third chip 230 and the secondterminals 82.

The first chip 210 is provided between the first terminals 81 and thesecond terminals 82. The direction from the first terminals 81 towardthe first chip 210 is aligned with the X-axis direction. The directionfrom the second terminals 82 toward the first chip 210 is aligned withthe X-axis direction.

The resin portion 51 covers the second chip 20 and the third chip 30.The resin portion 51 includes, the first resin region 51 a, the secondresin region 51 b, and the third resin region 51 c. The second chip 220is provided between the first resin region 51 a and the third resinregion 51 c. The third chip 230 is provided between the third resinregion 51 c and the second resin region 51 b. The third resin region 51c is provided between the second chip 220 and the third chip 230.

A power supply is supplied to the first power supply terminal 221 b ofthe second chip 220 via the first terminals 81 and the fifth conductivemember 243 and is supplied to the second power supply terminal 231 b ofthe third chip 230 via the second terminals 82 and the sixth conductivemember 244.

According to the electronic device 3 according to the fourth embodiment,the second chip 220 and the third chip 230 are connected to each othervia the optical waveguide 213 that is formed in the first chip 210. Thefirst optical element 211 converts an electrical signal from the secondchip 220 into an optical signal and outputs the optical signal to theoptical waveguide 213. Or, the first optical element 211 converts anoptical signal from the optical waveguide 213 into an electrical signaland outputs the electrical signal to the second chip 220. The secondoptical element 212 converts an electrical signal from the third chip230 into an optical signal and outputs the optical signal to the opticalwaveguide 213. Or, the second optical element 212 converts an opticalsignal from the optical waveguide 213 into an electrical signal andoutputs the electrical signal to the third chip 230.

According to such a fourth embodiment, high-speed signal transmission ina wide bandwidth is possible by using optical interconnects as a portionof the interconnects between the second chip 220 and the third chip 230.It is unnecessary to form a high-density fine conductor interconnectand/or an optical waveguide for the inter-chip connection in theinterconnect layer 240 in which the second chip 220 and the third chip230 are mounted; and the interconnect can be only a rough interconnectformable at the panel level having a large surface area. This makesthermal isolation between the second chip 220 and the third chip 230possible by using an optical waveguide in which a cost reduction,high-speed inter-chip communication, and signal transmission with lowloss even over long distances are possible.

Fifth Embodiment

FIG. 11A is a schematic cross-sectional view illustrating an electronicdevice 4 according to a fifth embodiment.

FIG. 12 is a schematic plan view showing an arrangement example of afirst chip 310 and the second chip 20 of the electronic device 4.

As shown in FIG. 11A, the electronic device 4 according to the fifthembodiment includes a first interconnect layer 340, the first chip 310,the second chip 20, the resin portion 51, the multiple first terminals81, and the multiple second terminals 82.

The first chip 310 includes a first region 310 a and a second region 310b. The second chip 20 includes the third region 20 a and the fourthregion 20 b.

The first chip 310 includes, for example, a memory element. The memoryelement is, for example, cache memory. The second chip 20 includes, forexample, a logic element.

The direction from the first region 310 a of the first chip 310 towardthe third region 20 a of the second chip 20 is aligned with the firstdirection. The first direction is aligned with the X-axis direction. Thesecond direction crosses the first direction. In the example, the seconddirection is orthogonal to the first direction and is aligned with theY-axis direction.

The direction from the first region 310 a of the first chip 310 towardthe fourth region 20 b of the second chip 20 crosses the first directionand the second direction. The direction from the second region 310 b ofthe first chip 310 toward the third region 20 a of the second chip 20crosses the first direction and the second direction.

The resin portion 51 covers at least a portion of the side surface ofthe second chip 20. The resin portion 51 includes the first resin region51 a and the second resin region 51 b. The second chip 20 is providedbetween the first resin region 51 a and the second resin region 51 b.Although the embodiment is shown in the example shown in FIG. 11A inwhich the surface of the second chip 20 opposite to the interconnectlayer 340 also is covered with the resin portion 51, the exposure fromthe resin portion 51 of the surface opposite to the interconnect layer340 is arbitrary. Also, although the configuration in the example shownin FIG. 11A includes the resin portion 51 disposed also at theperipheral portion of the second conductive member 21, the resin portion51 may not be at the peripheral portion of the second conductive member21; for example, a different insulating material may be at theperipheral portion of the second conductive member 21.

The first interconnect layer 340 is provided between the first region310 a of the first chip 310 and the third region 20 a of the second chip20, between the second region 310 b of the first chip 310 and the secondresin region 51 b, between the fourth region 20 b of the second chip 20and the first terminals 81, between the first resin region 51 a and thefirst terminals 81, and between the second resin region 51 b and thesecond terminals 82.

The first chip 310 includes a first conductive member 311. The firstconductive member 311 is, for example, a metal member and includes anelectrode terminal and a conductive layer.

The insulating portion 55 is provided between the first chip 310 and thefirst interconnect layer 340. For example, the insulating portion 55 ismade of a resin material or an inorganic material. For example, theinsulating portion 55 can be injected after connecting the firstconductive member 311 to the first interconnect layer 340. Or, aformation method may be used in which the insulating portion 55 ispre-formed in a region including the periphery of the first conductivemember 311; and the insulating portion 55 is connected to the firstinterconnect layer 340 simultaneously with the first conductive member311.

The second chip 20 includes the second conductive member 21. The secondconductive member 21 is, for example, a metal member. The secondconductive member 21 includes the first signal terminal 21 a, the firstpower supply terminal 21 b, and a conductive layer (not illustrated)connected to the first signal terminal 21 a and the first power supplyterminal 21 b.

The first interconnect layer 340 includes the insulating layer 45, athird conductive member 341, a fourth conductive member 343, and a sixthconductive member 344.

The insulating layer 45 is, for example, a resin layer. The insulatinglayer 45 is provided between the third conductive member 341, the fourthconductive member 343, and the sixth conductive member 344. Theinsulating layer 45 may be an inorganic insulating material.

The third conductive member 341 is provided between the first region 310a of the first chip 310 and the third region 20 a of the second chip 20and connects the first conductive member 311 of the first chip 310 andthe first signal terminal 21 a of the second chip 20. The thirdconductive member 341 extends along the Z-axis direction and is, forexample, a metal via. Many inter-chip interconnect connections arepossible by arranging the multiple third conductive members 341 in anarray configuration in the X-Y plane.

The fourth conductive member 343 is provided between the fourth region20 b of the second chip 20 and the first terminals 81 and connects thefirst power supply terminal 21 b of the second chip 20 and the firstterminals 81.

The sixth conductive member 344 connects the first conductive member 311of the first chip 310 and the second terminals 82.

The first chip 310 is provided between the first terminals 81 and thesecond terminals 82. The direction from the first terminals 81 towardthe first chip 310 is aligned with the X-axis direction. The directionfrom the second terminals 82 toward the first chip 310 is aligned withthe X-axis direction.

The first interconnect layer 340 is provided also between the firstresin region 51 a and the first terminals 81 and between the secondresin region 51 b and the second terminals 82.

Similarly to the electronic device 1 of the first embodiment shown inFIG. 1A described above, the electronic device 4 according to the fifthembodiment further includes the eighth conductive member 52, the ninthconductive member 53, and the semiconductor package device 60.

The electronic device 4 further includes a third chip 170 and a fourthchip 171. The third chip 170 and the fourth chip 171 include, forexample, an IPD (Integrated Passive Device) or a passive element. Thepassive element includes, for example, a discrete component such as acapacitor, an inductor, a resistance element, etc.

For example, the third chip 170 is connected to the third conductivemember 343; and, for example, the fourth chip 171 is connected to thesixth conductive member 344.

The first interconnect layer 340 is provided between the fourth region20 b of the second chip 20 and the third chip 170. The third chip 170 isprovided between the first terminals 81 and the first chip 310.

The first interconnect layer 340 is provided between the fourth chip 171and the second region 310 b of the first chip 310. The fourth chip 171is covered with the second resin region 51 b.

As shown in FIG. 11A and FIG. 12, the length along the X-axis directionof the first chip 310 may be shorter than the length along the X-axisdirection of the second chip 20.

The first conductive member 311 of the first chip 310 is electricallyconnected to the first signal terminal 21 a of the second chip 20 viathe third conductive member 341.

The power supply is supplied to the first power supply terminal 21 b ofthe second chip 20 via the first terminals 81 and the fourth conductivemember 343. Also, the power supply is supplied to the first chip 310 viathe second terminals 82 and the sixth conductive member 344.

According to the electronic device 4 according to the fifth embodiment,the first chip 310 and the second chip 20 can be connected to each othernot by an interconnect extending in a direction along the X-Y plane butby the third conductive member 341 having a via configuration extendingin the Z-axis direction. It is unnecessary to form a high-density fineinterconnect for the inter-chip connection in the first interconnectlayer 340; and the interconnect may be only an interconnect having arough line-and-space formable at the panel level having a large surfacearea. This makes a cost reduction possible.

For example, the first region 310 a of the first chip 310 including thememory element is substantially the memory interface region; and thefirst region 310 a opposes the second chip 20 with the firstinterconnect layer 40 interposed in the Z-axis direction. The first chip310 includes the second region 310 b that does not oppose the secondchip 20.

Such a chip layout makes it possible to widen the region where the firstterminals 81 are disposed and to reduce the distance between the firstterminals 81 and the first power supply terminal 21 b formed in thefourth region 20 b of the second chip 20. This reduces the sourceimpedance of the second chip 20. The decrease of the source impedancedeters the fluctuation of the power supply voltage and makes stableoperations possible.

The first chip 310 includes, for example, cache memory as a memoryelement. The semiconductor package device 60 includes, for example, DRAMas main memory having a larger memory capacity than the cache memory.The second chip 20 controls the first chip 310 and the semiconductorpackage device 60.

In such a configuration, compared to a configuration in which the cachememory is internally integrated in the second chip 20, cache memory thathas a large capacity can be embedded as a system inside one package; theimprovement of the system performance can be realized; and a costreduction of the inter-chip connection interconnect and stableelectrical power supply to the chips can be realized.

FIG. 11B is a schematic cross-sectional view of an electronic device 4′of another example of the fifth embodiment.

Compared to the electronic device 4 of FIG. 11A, the electronic device4′ further includes a second interconnect layer 540. The secondinterconnect layer 540 is provided between the first interconnect layer340 and multiple terminals 83. The first interconnect layer 340 isprovided between the second interconnect layer 540 and the resin portion51.

The terminals 83 are external terminals that connect the electronicdevice 4′ to an external circuit. The terminals 83 are, for example,solder balls. The terminals 83 may be metal pads or metal bumps.

The second interconnect layer 540 includes an insulating layer 545 and afifth conductive member 546.

The insulating layer 545 is, for example, a resin layer. The insulatinglayer 545 covers the first chip 310 and the third chip 170.

The fifth conductive member 546 is, for example, a metal member and isconnected to the fourth conductive member 343 and the sixth conductivemember 344 of the first interconnect layer 340 and to the terminals 83.

The insulating layer 545 includes an insulating portion 545 a providedbetween the first chip 310 and the terminals 83. The first chip 310 isprovided between the insulating portion 545 a and the first interconnectlayer 340.

The power supply is supplied to the second chip 20 via the terminals 83,the fifth conductive member 546 of the second interconnect layer 540,and the fourth conductive member 343 of the first interconnect layer340.

The power supply is supplied to the first chip 310 via the terminals 83,the fifth conductive member 546 of the second interconnect layer 540,and the sixth conductive member 344 of the first interconnect layer 340.

The multiple terminals 83 can be arranged over a wide region of thesecond interconnect layer 540 without constraints due to the arrangementposition of the first chip 310. This makes it possible to accommodatethe increase of the number of external input/output terminalsaccompanying the expanded function of the electronic device 4′.

Sixth Embodiment

FIG. 13 is a schematic cross-sectional view illustrating an electronicdevice 5 according to a sixth embodiment.

FIG. 14 is a schematic view showing the connectional relationshipbetween a first chip 410 and a second chip 520 of the electronic device5.

As shown in FIG. 13, the electronic device 5 according to the sixthembodiment includes an interconnect layer 440, the first chip 410, thesecond chip 520, the resin portion 51, and multiple third terminals 181.

The first chip 410 includes a conductive member 411; and the second chip520 includes a conductive member 521. The conductive member 411 and theconductive member 521 are, for example, metal members.

The resin portion 51 covers at least a portion of the side surface ofthe second chip 520. The side surface crosses the X-Y plane. The resinportion 51 includes the first resin region 51 a and the second resinregion 51 b. The second chip 520 is provided between the first resinregion 51 a and the second resin region 51 b. Although an embodiment isshown in the example shown in FIG. 13 in which the surface of the secondchip 520 opposite to the interconnect layer 440 also is covered with theresin portion 51, the exposure from the resin portion 51 of the surfaceopposite to the interconnect layer 440 is arbitrary. Also, although theconfiguration in the example shown in FIG. 13 includes the resin portion51 disposed also at the peripheral portion of the second conductivemember 521, the resin portion 51 may not be at, the peripheral portionof the second conductive member 521; and, for example, a differentinsulating material may be at the peripheral portion of the secondconductive member 521.

The interconnect layer 440 is provided between the first chip 410 andthe second chip 520, between the third terminals 181 and the second chip520, between the first resin region 51 a and the third terminals 181,and between the second resin region 51 b and the third terminals 181.

The insulating portion 55 is provided between the first chip 410 and theinterconnect layer 440. For example, the insulating portion 55 is madeof a resin material or an inorganic material. For example, theinsulating portion 55 can be injected after connecting the firstconductive member 411 to the interconnect layer 440. Or, a formation.method may be used in which the insulating portion 55 is pre-formed in aregion including the periphery of the first conductive member 411; andthe insulating portion 55 is connected to the interconnect layer 440simultaneously with the first conductive member 411.

The interconnect layer 440 includes the insulating layer 45, a firstconductive member 441, a second conductive member 442, and a thirdconductive member 443.

The insulating layer 45 is, for example, a resin layer. The insulatinglayer 45 is provided between the first conductive member 441, the secondconductive member 442, and the third conductive member 443.

The conductive member 411 of the first chip 410 is electricallyconnected to the conductive member 521 of the second chip 520 via thefirst conductive member 441 and the second conductive member 442.

The third terminals 181 are external terminals connecting the electronicdevice 5 to an external circuit. The third terminals 181 are, forexample, solder balls. The third terminals 181 may be metal pads ormetal bumps.

The first chip 410 is provided between the multiple third terminals 181.

The length along the X-axis direction of the first chip 410 is shorterthan the length along the X-axis direction of the second chip 520.

The interconnect layer 440 is provided also between the first resinregion 51 a and the third terminals 181 and between the second resinregion 51 b and the third terminals 181.

Similarly to the electronic device 1 of the first embodiment shown inFIG. 1A described above, the electronic device 5 according to the sixthembodiment further includes the eighth conductive member 52, the ninthconductive member 53, and the semiconductor package device 60.

As shown in FIG. 14, the first chip 410 includes a memory element 421and a first capacitor 422.

FIG. 15 is a schematic plan view showing the arrangement of a firstelement region 621 where the memory element 421 is disposed and a secondelement region 622 where the first capacitor 422 is disposed in thefirst chip 410.

The memory element 421 is, for example, DRAM. The DRAM includes atransistor 551 and a second capacitor 552.

The first capacitor 422 has the same structure as the second capacitor552 of the DRAM (e.g., a stacked capacitor, a trench capacitor, etc.).

In the example shown in FIG. 15, the second element region 622 isdisposed between two first element regions 621. An insulating separationportion 650 is provided between the first element region 621 and thesecond element region 622. The insulating separation portion 650 is, forexample, STI (Shallow Trench Isolation).

The insulating separation portion 650 interrupts the connection betweenthe memory element 421 and the first capacitor 422. The memory element421 and the first capacitor 422 are connected neither physically norelectrically.

The second chip 520 includes, for example, a logic element controllingthe memory element 421 of the first chip 410. As shown in FIG. 14, theconductive member 521 of the second chip 520 includes a first terminal521 a, a second terminal 521 b, and a fourth terminal 521 c.

The first terminal 521 a is a signal terminal; the second terminal 521 bis a power supply terminal; and the fourth terminal 521 c is a groundterminal.

The conductive member 411. of the first chip 410 includes an electrodeof the memory element 421 and an electrode of the first capacitor 422.

The memory element 421 of the first chip 410 is electrically connectedto the first terminal 521 a of the second chip 520 via the firstconductive member 441 of the interconnect layer 440.

The first capacitor 422 of the first chip 410 is electrically connectedto the second terminal 521 b and the fourth terminal 521 c of the secondchip 520 via the second conductive member 442 of the interconnect layer440.

The first capacitor 422 of the first chip 410 and the second terminal521 b and the fourth terminal 521 c of the second chip 520 areelectrically connected to the third terminals 181 via the thirdconductive member 443 of the interconnect layer 440.

According to the electronic device 5 according to the sixth embodiment,the first chip 410 and the second chip 520 can be connected to eachother not by an interconnect extending in a direction along the X-Yplane but by the first conductive member 441 and the second conductivemember 442 having via configurations extending in the Z-axis direction.It is unnecessary to form a high-density fine interconnect for theinter-chip connection in the interconnect layer 440; and theinterconnect can be only an interconnect having a rough line-and-spaceformable at the panel level having a large surface area. This makes acost reduction possible.

In the first chip 410, the first capacitor 422 that is integrated withthe memory element 421 is, for example, a decoupling capacitor connectedto the power supply line of the second chip 520 and suppresses thefluctuation of the power supply voltage of the second chip 520. Thismakes stable operations of the second chip 520 possible.

FIG. 16A is a schematic cross-sectional view showing the connectionalrelationship between the first chip 10, the second chip 20, and thethird chip 30 of an electronic device according to a seventh embodiment.

The electronic device according to the seventh embodiment has thestructure of the electronic device 1 shown in FIG. 1A in which thesignal transfer portion between the first chip 10 and the second chip 20and the signal transfer portion between the first chip 10 and the thirdchip 30 are not the conductive members 41 and 42, which are replacedwith an inductive coupling pair or a capacitive coupling pair.

The first chip 10 includes a first coupling element 11 d provided in thefirst region 10 a, and a second coupling element 11 e provided in thesecond region 10 b. The second chip 20 includes a third coupling element21 d provided in the third region 20 a. The third chip 30 includes afourth coupling element 31 d provided in the fifth region 30 a.

The insulating layer 45 of the interconnect layer 40 is provided betweenthe first coupling element 11 d and the third coupling element 21 d andbetween the second coupling element 11 e and the fourth coupling element31 d. The conductive members of the interconnect layer 40 between thefirst coupling element 11 d and the third coupling element 21 d andbetween the second coupling element 11 e and the fourth coupling element31 d may not be provided.

The direction from the first coupling element 11 d toward the thirdcoupling element 21 d is aligned with the Z-axis direction; and thedirection from the second coupling element 11 e toward the fourthcoupling element 31 d is aligned with the Z-axis direction. Thedirection from the first coupling element 11 d toward the secondcoupling element 11 e is aligned with the X-axis direction; and thedirection from the third coupling element 21 d toward the fourthcoupling element 31 d is aligned with the X-axis direction.

For example, the first chip 10 can be fixed to the interconnect layer 40by a bonding agent. Or, the first chip 10 can be directly coupled to theinterconnect layer 40 by utilizing a dehydrating condensation reaction.

The first coupling element 11 d, the second coupling element 11 e, thethird coupling element 21 d, and the fourth coupling element 31 d areinductive coupling elements or capacitive coupling elements.

The first coupling element 11 d of the first chip 10 and the thirdcoupling element 21 d of the second chip 20 have inductive coupling orcapacitive coupling. The second coupling element 11 e of the first chip10 and the fourth coupling element 31 d. of the third chip 30 haveinductive coupling or capacitive coupling.

Similarly to the first chip 10 of the first embodiment shown in FIG. 1D,the first chip 10 further includes the conductive layer 11 b. Theconductive layer 11 b electrically connects between the first couplingelement 11 d and the second coupling element 11 e.

Signals are transmitted between the second chip 20 and the third chip 30via the inductive coupling or the capacitive coupling between the firstcoupling element 11 d and the third coupling element 21 d, via theconductive layer 11 b of the first chip 10, and via the inductivecoupling or the capacitive coupling between the second coupling element11 e and the fourth coupling element 31 d.

The seventh embodiment may include the following configuration:

-   -   an electronic device, including:        -   a first chip including a first coupling element, a second            coupling element, and a first conductive member;        -   a second chip including a third coupling element;        -   a third chip including a fourth coupling element; and        -   an insulating layer provided between the first coupling            element and the third coupling element and between the            second coupling element and the fourth coupling element,    -   the first coupling element and the third coupling element having        inductive coupling or capacitive coupling, the second coupling        element and the fourth coupling element having inductive        coupling or capacitive coupling,    -   the first conductive member electrically connecting the first        coupling element and the second coupling element.

FIG. 16B is a schematic cross-sectional view showing the connectionalrelationship between the first chip 310 and the second chip 20 of anelectronic device according to an eighth embodiment.

The electronic device according to the eighth embodiment has thestructure of the electronic device 4 shown in FIG. 11A in which thesignal transfer portion between the first chip 310 and the second chip20 is not the conductive member 341, which is replaced with an inductivecoupling pair or a capacitive coupling pair.

The first chip 310 includes a first coupling element 311 a provided inthe first region 310 a. The second chip 20 includes a second couplingelement 21 e provided in the third region 20 a.

The insulating layer 45 of the interconnect layer 340 is providedbetween the first coupling element 311 a and the second coupling element21 e. The conductive members of the interconnect layer 340 are notprovided between the first coupling element 311 a and the secondcoupling element 21 e.

The direction from the first coupling element 311 a toward the secondcoupling element 21 e is aligned with the Z-axis direction.

For example, the first chip 310 can be fixed to the interconnect layer340 by a bonding agent. Or, the first chip 310 can be directly coupledto the interconnect layer 340 by utilizing a dehydrating condensationreaction.

The first coupling element 311 a and the second coupling element 21 eare inductive coupling elements or capacitive coupling elements.

The first coupling element 311 a of the first chip 310 and the secondcoupling element 21 e of the second chip 20 have inductive coupling orcapacitive coupling.

The signals are transmitted between the first chip 310 and the secondchip 20 via the inductive coupling or the capacitive coupling betweenthe first coupling element 311 a and the second coupling element 21 e.

The eighth embodiment may include the following configuration:

-   -   an electronic device, including:        -   a first chip including a first coupling element;        -   a second chip including a second coupling element; and        -   an insulating layer provided between the first coupling            element and the second coupling element,    -   the first coupling element and the second coupling element        having inductive coupling or capacitive coupling.

FIG. 17 is a schematic cross-sectional view of an electronic device V ofa modification of the electronic device 1 shown in FIG. 1A.

The electronic device 1′ has the structure of the electronic device 1shown in FIG. 1A in which the second interconnect layer 540 shown inFIG. 11B is provided. The multiple terminals 83 can be arranged over awide region of the second interconnect layer 540 without constraints dueto the arrangement position of the first chip 10. This makes it possibleto accommodate the increase of the number of external input/outputterminals accompanying the expanded function of the electronic device1′.

FIG. 18 is a schematic cross-sectional view of an electronic device 2′of a modification of the electronic device 2 shown in FIG. 7.

The electronic device 2′ has the structure of the electronic device 2shown in FIG. 7 in which the second interconnect layer 540 shown in FIG.11B is provided. The multiple terminals 83 can be arranged over a wideregion of the second interconnect layer 540 without constraints due tothe arrangement position of the first chip 110. This makes it possibleto accommodate the increase of the number of external input/outputterminals accompanying the expanded function of the electronic device1′.

FIG. 19 is a schematic cross-sectional view of an electronic device 3′of a modification of the electronic device 3 shown in FIG. 10.

The electronic device 3′ has the structure of the electronic device 3shown in FIG. 10 in which the second interconnect layer 540 shown inFIG. 11B is provided. The multiple terminals 83 can be arranged over awide region of the second interconnect layer 540 without constraints dueto the arrangement position of the first chip 210. This makes itpossible to accommodate the increase of the number of externalinput/output terminals accompanying the expanded function of theelectronic device 1′.

FIG. 20 is a schematic cross-sectional view of an electronic device 5′of a modification of the electronic device 5 shown in FIG. 13.

The electronic device 5′ has the structure of the electronic device 5shown in FIG. 13 in which the second interconnect layer 540 shown inFIG. 11B is provided. The multiple terminals 83 can be arranged over awide region of the second interconnect layer 540 without constraints dueto the arrangement position of the first chip 410. This makes itpossible to accommodate the increase of the number of externalinput/output terminals accompanying the expanded function of theelectronic device 1′.

FIG. 21 is a schematic cross-sectional view of an electronic deviceaccording to a ninth embodiment.

The electronic device according to the ninth embodiment has thestructure of any of the electronic devices 1 to 5 described above inwhich a third interconnect layer 700 is provided.

The third interconnect layer 700 includes a conductive member 701including a metal interconnect, a metal via, and a metal pad. Any of theelectronic devices 1 to 5 is mounted on the third interconnect layer 700via the multiple terminals 81. The terminals 81 are connected to theconductive member 701 of the third interconnect layer 700.

Multiple terminals 84 are provided on the opposite face of the mountingsurface of the third interconnect layer 700 for the electronic devices 1to 5. The terminals 84 are, for example, solder balls. The terminals 84are connected to the conductive member 701 of the third interconnectlayer 700. The multiple terminals 84 can be arranged over a wide regionof the third interconnect layer 700 without constraints due to thearrangement position of the first chip of the electronic devices 1 to 5described above. This makes it possible to accommodate the increase ofthe number of external input/output terminals accompanying the expandedfunction of the electronic device.

An example will now be described with reference to FIG. 22 to FIG. 26 inwhich the electronic device of the second embodiment shown in FIG. 7 toFIG. 9 described above is applied to a large-scale system.

FIG. 22 is a schematic view showing the arrangement and the connectionsof the first chips 110 and 110′, the second chips 20, the third chips30, and the interconnect layer 40. The interconnect layer 40 isschematically illustrated by one straight line.

FIG. 23 is a schematic plan view of the electronic device shown in FIG.22.

FIG. 24 is a schematic view in which the positions of the second chips20 and the positions of the third chips 30 of FIG. 23 are interchanged.

According to the example shown in FIG. 22 to FIG. 24, the multiple firstchips 110 and 110′, the multiple second chips 20, and the multiple thirdchips 30 are mounted to the interconnect layer 40. The third chips 30can function as shared memory between mutually-adjacent second chips 20.

FIG. 25 is a schematic plan view showing an application example of theelectronic device of the second embodiment to a neural network.

The input/output information, the connection information, etc., betweenthe artificial neurons (the nodes) is stored in the second memoryelements 115 of the third chips 30; and the logic elements of the secondchips 20 execute calculation processing based on the information. Alarge-scale parallel neural network can be realized by arranging thesecond chips 20 and the third chips 30 in a matrix configuration and bymutually connecting with the first chips 10, 110, and 110′. The firstchips may be used to store temporary calculation information in the casewhere memory elements are included in the first chips.

The data transfer to distal nodes may be executed by using theinterconnects of the interconnect layer 40 or by sharing the memory ofthe third chips 30. By uniformly mixing and densely connecting themultiple memory elements and the multiple logic elements, a scalablesystem can be configured while minimizing the data transfer energy.

FIG. 26 is a descriptive view of a neural network.

The neural network is a model that has problem solving ability in whichartificial neurons (nodes) are formed in a network by the connections ofsynapses; and the connection strengths of the synapses are changed bylearning. As shown in FIG. 26, a neural network that is connected inmultiple layers is called a deep neural network and has been utilized invarious fields in recent years.

FIG. 27 is a schematic view showing an application example of theelectronic device of the second embodiment to a neural network.

The input/output information, the connection information, etc., betweenthe artificial neurons (the nodes) is stored in the second memoryelements 115 of the third chips 30 and shared between the multiplesecond chips 20; and the logic elements of the second chips 20 executecalculation processing based on the information.

In the processing of a neural network using a conventional GPU (GraphicsProcessing Unit), etc., it. is necessary to repeat the data transferbetween the memory elements and the logic elements for the calculationfor each layer; and there is a limit to the energy efficiency and theprocessing performance.

In the embodiment as shown in FIG. 27, by spatially dispersing thecalculation processing of multiple layers and by executing inmulti-parallel, it is possible to approach the information processingperformance and the efficiency of an actual brain.

FIG. 28 is a schematic plan view showing the full grid tile structure ofthe first chips 110 and 110′, the second chips 20, and the third chips30.

The full grid tile structure is formed by the multiple second chips 20and the multiple third chips 30 being densely connected by the multiplefirst chips 110 and 110′.

The full grid tile structure shown in FIG. 28 also is applicable to aneural network as shown in FIG. 29.

Compared to the configuration shown in FIG. 25, the configuration shownin FIG. 28 can improve the calculation performance and increase theneural network processing efficiency per unit surface area.

The embodiments described above may include the following configuration.

The interconnect layers 40, 240, 340, 440, and 540 are aligned with aplane including the second direction and a third direction. The seconddirection is aligned with the X-axis direction; and the third directioncrosses the second direction. For example, the third direction isorthogonal to the second direction and is aligned with the Y-axisdirection.

The multiple first terminals 81, the multiple second terminals 82, themultiple third terminals 181, and the multiple terminals 83 describedabove are arranged in the second direction and the third direction in aplane including the second direction and the third direction. In otherwords, the multiple first terminals 81, the multiple second terminals82, the multiple third terminals 181, and the multiple terminals 83 arearranged in an array configuration in a plane including the seconddirection and the third direction.

The conductive members 41 and 42, 241, 242, 341, 441, and 442 describedabove are aligned with the first direction crossing the plane recitedabove. For example, the conductive members 41 and 42, 241, 242, 341,441, and 442 are aligned with a direction substantially perpendicular tothe plane recited above.

The first chip 10 of the embodiment shown in FIGS. 1A and 1B is anelectrical interconnect member that has a chip configuration includingthe first conductive member 11 electrically connecting the second chip20 and the third chip 30 and does not include a memory element, atransistor, or a passive element.

The first chip 310 or the second chip 20 shown in FIG. 11A, FIG. 11B,and FIG. 16B includes a memory element.

FIG. 30 is a schematic cross-sectional view of an example of the thirdchip 30 of the above embodiments.

The third chip 30 has a stacked memory structure including a pluralityof memory chips 32 and a logic chip 33. The memory chips 32 are stackedon the logic chip 33. Each of the memory chips 32 includes the secondmemory element 115 shown in FIG. 8A to FIG. 9. The memory chips 32 areconnected each other through a plurality of metal pads or metal bumps34. The memory chips 32 are electrically connected to the logic chip 33through the metal pads or metal bumps 34. The logic chip 33 iselectrically connected to the signal terminals 31 a, 31 b of the thirdchip 30 shown in FIG. 8A to FIG. 9. The memory chips 32 are molded by aresin 35.

Note 1

An electronic device, comprising:

a first chip including a first optical element, a second opticalelement, and an optical waveguide optically coupled to the first opticalelement and the second optical element;

a second chip including a first conductive member, a first region, and asecond region;

a third chip including a second conductive member, a third region, and afourth region;

a first terminal;

a second terminal; and

an interconnect layer provided between the first optical element of thefirst chip and the first region of the second chip, between the secondoptical element of the first chip and the third region of the thirdchip, between the first terminal and the second region of the secondchip, and between the second terminal and the fourth region of the thirdchip,

the interconnect layer including

-   -   a third conductive member provided between the first optical        element of the first chip and the first region of the second        chip, the third conductive member connecting the first optical        element of the first chip and the first conductive member of the        second chip, and    -   a fourth conductive member provided between the second optical        element of the first chip and the third region of the third        chip, the fourth conductive member connecting the second optical        element of the first chip and the second conductive member of        the third chip,

the first chip being provided between the first terminal and the secondterminal.

Note 2

The electronic device according to Note 1, wherein

the second chip further includes a first power supply terminal,

the third chip further includes a second power supply terminal, and

the interconnect layer further includes a fifth conductive member and asixth conductive member, the fifth conductive member connecting thefirst power supply terminal and the first terminal, the sixth conductivemember connecting the second power supply terminal and the secondterminal.

Note 3

An electronic device, comprising:

a first chip including a memory element and a first capacitor; and

a second chip including a first terminal and a second terminal, thefirst terminal being connected to the memory element, the secondterminal being connected to the first capacitor.

Note 4

The electronic device according to Note 3, further comprising aninterconnect layer provided between the first chip and the second chip,

the interconnect layer including

-   -   a first conductive member provided between the memory element of        the first chip and the first terminal of the second chip, the        first conductive member connecting the memory element of the        first chip and the first terminal of the second chip, and    -   a second conductive member provided between the first capacitor        of the first chip and the second terminal of the second chip,        the second conductive member connecting the first capacitor of        the first chip and the second terminal of the second chip.

Note 5

The electronic device according to Note 4, further comprising a thirdterminal,

the interconnect layer further including a third conductive memberprovided between the third terminal and the second terminal of thesecond chip, the third conductive member connecting the third terminaland the second terminal of the second chip.

Note 6

The electronic device according to any one of Notes 3 to 5, wherein thefirst chip further includes an insulating separation portion providedbetween the memory element and the first capacitor.

Note 7

The electronic device according to any one of Notes 3 to 6, wherein thememory element is DRAM (Dynamic Random Access Memory) including a secondcapacitor.

Note 8

An electronic device, comprising:

a first chip including a first conductive member, a first region, and asecond region;

a second chip including a second conductive member, a third region, anda fourth region;

a third chip including a third conductive member, a fifth region, and asixth region;

a first terminal;

a second terminal; and

an interconnect layer provided between the first region of the firstchip and the third region of the second chip, between the second regionof the first chip and the fifth region of the third chip, between thefirst terminal and the fourth region of the second chip, and between thesecond terminal and the sixth region of the third chip,

the interconnect layer including

-   -   a fourth conductive member provided between the first region of        the first chip and the third region of the second chip, the        fourth conductive member connecting the first conductive member        of the first chip and the second conductive member of the second        chip, and    -   a fifth conductive member provided between the second region of        the first chip and the fifth region of the third chip, the fifth        conductive member connecting the first conductive member of the        first chip and the third conductive member of the third chip,

the first chip being provided between the first terminal and the secondterminal.

Note 9

The electronic device according to Note 8, wherein the first chip is anelectrical interconnect member connecting the second chip and the thirdchip via the first conductive member, the fourth conductive member, andthe fifth conductive member.

Note 10

The electronic device according to Note 9, wherein the first chip doesnot include a substrate.

Note 11

The electronic device according to Note 9, wherein the third chipincludes a memory element.

Note 12

The electronic device according to Note 8, wherein the first chipfurther includes a first memory element connected to the fourthconductive member.

Note 13

The electronic device according to Note 12, wherein the third chipfurther includes a second memory element connected to the fifthconductive member.

Note 14

The electronic device according to Note 13, wherein a memory capacity ofthe second memory element is larger than a memory capacity of the firstmemory element.

Note 15

The electronic device according to Note 13 or 14, wherein the first chipfurther includes a controller connected to the fifth conductive member.

Note 16

The electronic device according to any one of Notes 8 to 15, wherein

the second chip further includes a first power supply terminal,

the third chip further includes a second power supply terminal, and

the interconnect layer further includes a sixth conductive member and aseventh conductive member, the sixth conductive member connecting thefirst power supply terminal and the first terminal, the seventhconductive member connecting the second power supply terminal and thesecond terminal.

Note 17

The electronic device according to Note 16, wherein

the interconnect layer further includes an insulating layer providedbetween the fourth conductive member and the sixth conductive member andbetween the fifth conductive member and the seventh conductive member,

the fourth conductive member and the sixth conductive member areinsulatively separated, and

the fifth conductive member and the seventh conductive member areinsulatively separated.

Note 18

An electronic device, comprising:

a first chip including a first conductive member, a first region, and asecond region;

a second chip including a second conductive member, a third region, anda fourth region;

a resin portion including a first resin region and a second resinregion;

a terminal; and

a first interconnect layer provided between the first region of thefirst chip and the third region of the second chip, between the secondregion of the first chip and the first resin region, between theterminal and the fourth region of the second chip, and between theterminal and the second resin region,

the first interconnect layer including a third conductive memberprovided between the first region of the first chip and the third regionof the second chip, the third conductive member connecting the firstconductive member of the first chip and the second conductive member ofthe second chip,

the second chip being provided between the first resin region and thesecond resin region of the resin portion.

Note 19

The electronic device according to Note 18, wherein

the second chip further includes a power supply terminal, and

the first interconnect layer further includes a fourth conductive memberconnecting the power supply terminal and the terminal.

Note 20

The electronic device according to Note 18 or 19, further comprising asecond interconnect layer provided between the first interconnect layerand the terminal,

the second interconnect layer including a fifth conductive member and aninsulating portion, the fifth conductive member being connected to theterminal, the insulating portion being provided between the terminal andthe first chip,

the first chip being provided between the insulating portion and thefirst interconnect layer.

Note 21

The electronic device according to any one of Notes 18 to 20, whereinthe first chip or the second chip includes a memory element.

Note 22

An electronic device, comprising:

a first chip including a first connection region and a second connectionregion;

a second chip including a third connection region facing the firstconnection region of the first chip; and

a third chip including a fourth connection region facing the secondconnection region of the first chip,

the first chip including a first memory element and a plurality of firstinterconnects, the first chip including a plurality of first signalterminals provided in the first connection region and electricallyconnected to the first memory element, the plurality of firstinterconnects being provided in the first connection region and thesecond connection region,

the second chip including a plurality of second signal terminals and aplurality of third signal terminals, the plurality of second signalterminals being provided in the third connection region, the pluralityof third signal terminals being provided in the third connection region,

the third chip including a second memory element and a plurality offourth signal terminals electrically connected to the second memoryelement, the plurality of fourth signal terminals being provided in thefourth connection region,

the second signal terminals of the second chip being connected to thefirst terminals of the first chip,

the first interconnects being connected to the third signal terminals ofthe second chip and the fourth signal terminals of the third chip.

Note 23

The electronic device according to Note 22, further comprising aninterconnect layer provided between the first chip and the second chip,and between the first chip and the third chip,

the interconnect layer including

-   -   a plurality of first metal vias connecting the second signal        terminals of the second chip and the first signal terminals of        the first chip,    -   a plurality of second metal vias connecting the first        interconnects and the third signal terminals of the second chip,    -   a plurality of third metal vias connecting the first        interconnects and the fourth signal terminals of the third chip,        and    -   a plurality of second interconnects connecting the second chip        and the third chip to an outside.

Note 24

The electronic device according to Note 23, wherein a minimum spacing ofthe multiple first interconnects provided in the first chip is smallerthan a minimum spacing of the multiple second interconnects provided inthe interconnect layer.

Note 25

The electronic device according to any one of Notes 22 to 24, wherein amemory capacity of the second memory element is larger than a memorycapacity of the first memory element.

Hereinabove, exemplary embodiments of the invention are described withreference to specific examples. However, the embodiments of theinvention are not limited to these specific examples. For example, oneskilled in the art may similarly practice the invention by appropriatelyselecting specific configurations of components included in electronicdevices such as interconnect layers, electrical elements, opticalelements, resin portions, etc., from known art. Such practice isincluded in the scope of the invention to the extent that similareffects thereto are obtained.

Further, any two or more components of the specific examples may becombined within the extent of technical feasibility and are included inthe scope of the invention to the extent that the purport of theinvention is included.

Moreover, all electronic devices, and methods for manufacturing the samepracticable by an appropriate design modification by one skilled in theart based on the electronic devices, and the methods for manufacturingthe same described above as embodiments of the invention also are withinthe scope of the invention to the extent that the purport of theinvention is included.

Various other variations and modifications can be conceived by thoseskilled in the art within the spirit of the invention, and it isunderstood that such variations and modifications are also encompassedwithin the scope of the invention.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modification as would fall within the scope andspirit of the inventions.

1-18. (canceled)
 19. An electronic device, comprising: two or more firstchips, each first chip including an interconnect member; three or morechips including at least one second chip and at least one third chip,the second chip including a second conductive member, the third chipincluding a third conductive member, the second conductive member of thesecond chip being electrically connected to the third conductive memberof the third chip via the interconnect member of one first chip; and aninterconnect layer provided between the first chip and the second chip,and between the first chip and the third chip, the interconnect layerbeing electrically connected to the interconnect member, the secondconductive member, and the third conductive member.
 20. The deviceaccording to claim 19, wherein the first chip includes a memory element.21. The device according to claim 19, wherein the second chip includes alogic element.
 22. The device according to claim 19, wherein the thirdchip includes a memory element.
 23. The device according to claim 19,wherein the second chip includes a logic element, and the third chipincludes a memory element.
 24. The device according to claim 19, furthercomprising a resin portion covering the second chip and the third chip.25. The device according to claim 19, wherein the first chip does notinclude a substrate.
 26. An electronic device, comprising: a first chipincluding a first region and a second region; a second chip including athird region and a fourth region; and a third chip including a fifthregion and a sixth region; wherein the second chip and the third chipare connected to each other via an optical waveguide on the first chip,and wherein the third region toward to the first region is aligned witha first direction, and the fifth region toward to the second region isaligned with the first direction, the first direction crossing a seconddirection from the second chip toward the third chip.
 27. The deviceaccording to claim 26, further comprising an interconnect layer providedbetween the first chip and the second chip, and between the first chipand the third chip.
 28. An electronic device, comprising: two or moresecond chips, each second chip including a second conductive member, andan artificial neuron; a third chip including a third conductive member,and a memory element shared by at least two second chips; and a firstchip including an interconnect member connected to the second conductivemember of the second chip and the third conductive member of the thirdchip, the second conductive member of the second chip being electricallyconnected to the third conductive member of the third chip, aninput/output information and a connection information between theartificial neurons being stored in the memory element of the third chip,and the second chip executing calculation processing based on theinformation stored in the memory element of the third chip.
 29. Thedevice according to claim 28, further comprising an interconnect layerprovided between the first chip and the second chip, and between thefirst chip and the third chip, the interconnect layer being electricallyconnected to the interconnect member, the second conductive member, andthe third conductive member.
 30. The device according to claim 29,further comprising a first terminal and a second terminal, the firstterminal and the second terminal being electrically connected to theinterconnect layer, the first chip being provided between the firstterminal and the second terminal.
 31. The device according to claim 29,wherein the artificial neuron is composed of a logic element.
 32. Thedevice according to claim 29, further comprising a resin portioncovering the second chip and the third chip.
 33. The device according toclaim 29, wherein two or more first chips, two or more second chips, andtwo or more third chips are arranged in a grid tile structure.
 34. Thedevice according to claim 29, wherein the first chip does not include asubstrate.
 35. The device according to claim 30, wherein the artificialneuron is composed of a logic element.
 36. The device according to claim30, further comprising a resin portion covering the second chip and thethird chip.
 37. The device according to claim 30, wherein two or morefirst chips, two or more second chips, and two or more third chips arearranged in a grid tile structure.
 38. The device according to claim 30,wherein the first chip does not include a substrate.